CPU feature flags

These are the explanations for the CPU flags available in Linux under Hardware information.

CPU flag	Flag meaning
3DNOW	A multimedia extension created by AMD for its processors, based on/almost equivalent to Intel's MMX extensions.
3DNOWEXT	3DNOW Extended. Also known as AMD's 3DNow! Enhanced/3DNow! Extensions.
APIC	Advanced Programmable Interrupt Controller.
CLFSH/CLFlush	Cache Line Flush.
CMOV	Conditional Move/Compare Instruction.
CMP_Legacy	Register showing the CPU is not Hyper-Threading capable.
Constant_TSC	On Intel Pentium 4's, the TSC runs with constant frequency independent of CPU frequency when EST is used.
CR8Legacy	Unknown
CX8	CMPXCHG8B Instruction (Compare and exchange 8 bytes. Also known as F00F, which is an abbreviation of the hexadecimal encoding of an instruction that exhibits a design flaw in the majority of older Intel Pentium CPU's).
CX16	CMPXCHG16B Instruction (CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for high resolution counters that could be updated by multiple processors (or cores). Without CMPXCHG16B the only way to perform such an operation is by using a critical section).
DE	Debugging Extensions.
DS	Debug Store.
DS_CPL	CPL qualified Debug Store (whatever CPL might mean in this context).
DTS	Could mean either Debug Trace Store or Digital Thermal Sensor, depending on source.
EIST/EST	Enhanced Intel SpeedStep Technology.
EPT	Extended Page Tables (Intel, similar to NPT on AMD).
FID	Frequency IDentifier.
FPU	x87 Floating Point Unit built into the CPU. This is where most mathematically intense calculations take place. Used to be a separate chip on the 80486SX and earlier (called the 80487 or 80387, etc. 80486DX had FPU built-in as well). All Pentium CPUs and later have this functionality built in.
FXSR	FXSAVE/FXRSTOR. (The FXSAVE instruction writes the current state of the x87 FPU, MMX technology, Streaming SIMD Extensions, and Streaming SIMD Extensions 2 data, control, and status registers to the destination operand. The destination is a 512-byte memory location. FXRSTOR will restore the state saves).
FXSR_OPT	Unknown
HT	Hyper-Transport. Note that the same abbreviation might is also used to indicate Hyper-Threading (see below).
HTT/HT	Hyper-Threading. An Intel technology that allows quasi-parallel execution of different instructions on a single core. The single core is seen by applications as if it were two (or potentially more) cores. However, two true CPU cores are almost always faster than a single core with HyperThreading. This flag indicates support in the CPU when checking the flags in /proc/cpuinfo on Linux systems.
HVM	Hardware support for virtual machines (Xen abbreviation for AMD SVM / Intel VMX).
LAHF_LM	Load Flags into AH Register, Long Mode.
LM	Long Mode (64bit Extensions, AMD's AMD64 or Intel's EM64T).
MCA	Machine Check Architecture.
MCE	Machine Check Exception.
MMX	It is rumoured to stand for MultiMedia eXtension or Multiple Math or Matrix Math eXtension, but officially it is a meaningless acronym trademarked by Intel.
MMXEXT	MMX Extensions – an enhanced set of instructions compared to MMX.
MNI	Modular Network Interface or Merom New Instruction (see SSSE3).
MON/MONITOR	CPU Monitor.
MSR	RDMSR and WRMSR Support.
MTRR	Memory Type Range Register.
NPT	Nested Page Tables (AMD, similar to EPT on Intel).
NX	No eXecute, a flag that can be set on memory pages to disable execution of code in these pages.
PAE	Physical Address Extensions. PAE is the added ability of the IA32 processor to address more than 4 GB of physical memory using Intel's 36bit page addresses instead of the standard 32bit page addresses to access a total of 64gibibytes of RAM. Most AMD chips support PAE as well. PAE is the second method supported to access memory above 4 GB (PSE36 being the first); this method has been widely implemented. PAE maps up to 64 GB of physical memory into a 32-bit (4 GB) virtual address space using either 4-KB or 2-MB pages. The Page directories and the page tables are extended to 8 byte formats, allowing the extension of the base addresses of page tables and page frames to 24 bits (from 20 bits). This is where the extra four bits are introduced to complete the 36-bit physical address. Windows supports PAE with 4-KB pages. PAE also supports a mode where 2-MB pages are supported. Many of the UNIX operating systems rely on the 2 MB-page mode. The address translation is done without the use of page tables (the PDE supplies the page frame address directly).
PAT	Page Attribute Table.
PBE	Pending Break Encoding.
PGE	PTE Global Bit.
PNI	Prescott New Instruction. This was the codename for SSE3 before it was released on the Intel Prescott processor (which was later added to the Pentium 4 family name).
PSE	Page Size Extensions (See PSE36).
PSE36	Page Size Extensions 36. IA-32 supports two methods to access memory above 4 GB (32 bits). PSE (Page Size Extension) was the first method, which shipped with the Pentium II. This method offers a compatibility advantage because it kept the PTE (page table entry) size of 4 bytes. However, the only practical implementation of this is through a driver. This approach suffers from significant performance limitations, due to a buffer copy operation necessary for reading and writing above 4 GB. PSE mode is used in the PSE 36 RAM disk usage model. PSE uses a standard 1K directory and no page tables to extend the page size 4-MB (eliminating one level of indirection for that mode). The Page Directory Entries (PDE) contains 14 bits of address, and when combined with the 22-bit byte index, yields the 36 bits of extended physical address. Both 4-KB and 4-MB pages are simultaneously supported below 4 GB, with the 4-KB pages supported in the standard way. Note that pages located above 4 GB must use PSE mode (with 4-MB page sizes).
SEP	SYSENTER and SYSEXIT.
SS	Self-Snoop.
SSE	Streaming SIMD Extensions. Developed by Intel for its Pentium III but also implemented by AMD processors from Athlon XP onwards.
SSE2	Streaming SIMD Extensions 2 (An additional 144 SIMDs). Introduced by Intel Pentium 4 and on AMD since Athlon 64.
SSE3	Streaming SIMD Extensions 3 (An additional 13 instructions). Introduced with “Prescott” revision Intel Pentium 4 processors. AMD introduced SSE3 with the Athlon 64 "Venice" revision.
SSSE3	Supplemental Streaming SIMD Extension 3 (SSSE3 contains 16 new discrete instructions over SSE3). Introduced on Intel Core 2 Duo processors. No AMD chip supports SSSE3 yet.
SSE4	Streaming SIMD Extentions 4. Introduced with "Nehalem" processor in 2008. Also known as "Nehalem New Instructions" (NNI).
SSE4_1	Streaming SIMD Extentions 4.1.
SSE4_2	Streaming SIMD Extentions 4.2.
SVM	Secure Virtual Machine. (AMD's virtualization extensions to the 64-bit x86 architecture, equivalent to Intel's VMX, both also known as HVM in the Xen hypervisor).
SYSCALL	System Call (the mechanism used by an application program to request service from the operating system).
TM	Thermal Monitor.
TM2	Thermal Monitor 2.
TNI	Tejas New Instruction. See SSSE3.
TPR	Task Priority Register.
TPR_SHADOW	Shadowed Task Priority Registers (for virtualization).
TS	Thermal Sensor.
TSC	Time Stamp Counter.
TTP	Thermal Trip.
VID	Voltage IDentifier
VME	Virtual-8086 Mode Enhancement.
VMX	Intel's equivalent to AMD's SVM.
VNMI	Virtual NMI (non-maskable interrupts) (for virtualization).
VPID	Virtual Processor ID (for virtualization).
XTPR	TPR register chipset update control messenger. Part of the APIC code.